View D2498_5452103.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1 ? e00x63-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxD2498r 48 pin lqfp (plastic) timing generator for frame readout ccd image sensor description the cxD2498r is a timing generator ic which generates the timing pulses for performing frame readout using the icx282 ccd image sensor. features ? base oscillation frequency 45mhz electronic shutter function supports various drive modes such as draft and af mode horizontal driver for ccd image sensor vertical driver for ccd image sensor applications digital still cameras structure silicon gate cmos ic applicable ccd image sensors icx282 (type 2/3, 5070k pixels) absolute maximum ratings supply voltage v dd v ss ? 0.3 to +7.0 v vl ?10.0 to v ss v vh vl ? 0.3 to +26.0 v input voltage v i v ss ? 0.3 to v dd + 0.3 v output voltage v o1 v ss ? 0.3 to v dd + 0.3 v v o2 vl ? 0.3 to v ss + 0.3 v v o3 vl ? 0.3 to vh + 0.3 v operating temperature topr ?20 to +75 c storage temperature tstg ?55 to +150 c recommended operating conditions supply voltage v dd a, v dd b, v dd c 3.0 to 3.6 v vm 0.0 v vh 14.5 to 15.5 v vl ?7.0 to ?8.0 v operating temperature topr ?20 to +75 c
? 2 ? cxD2498r block diagram 35 34 43 38 42 40 5 4 24 23 22 21 17 19 18 9 15 13 12 10 16 11 8 26 25 30 v1b v1c v2 v1a id/exp wen v ss 4 adclk obclp clpdm pblk v dd 4 xshd xshp v ss 2 h2b h2a h1b h1a v dd 3 v dd 2 rg vd hd 7 29 1 v ss 1 36 v ss 5 v dd 5 v dd 1 mcko cko cki pulse generator 2 27 28 test2 test1 rst 20 45 37 41 47 46 44 vl vm vh v3c v3b v3a 39 v4 48 sub 31 32 33 sen sck ssi register v driver 6 ssgsl 3 sncsl 1/2 14 v ss 3 selector selector latch ssg vco
? 3 ? cxD2498r pin configuration ? groups of pins enclosed in the figure indicate sections for which power supply separation is possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 h2a v ss 3 h2b v dd 3 v dd 4 xshp xshd pblk clpdm obclp adclk v ss 4 cko cki test1 test2 v dd 5 mcko ssi sck sen vd hd v ss 5 h1b v dd 2 h1a rg ssgsl v dd 1 v ss 2 wen id/exp sncsl rst v ss 1 sub v3c v3b vl v3a v1b v1c vh v1a v4 v2 vm
? 4 ? cxD2498r pin description pin no. symbol i/o description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 v ss 1 rst sncsl id/exp wen ssgsl v dd 1 rg v ss 2 h1a v dd 2 h1b h2a v ss 3 h2b v dd 3 v dd 4 xshp xshd pblk clpdm obclp adclk v ss 4 cko cki test1 test2 v dd 5 mcko ssi ? i i o o i ? o ? o ? o o ? o ? ? o o o o o o ? o i i i ? o i gnd internal system reset input. high: normal operation, low: reset control normally apply reset during power-on. schmitt trigger input control input used to switch sync system. high: cki sync, low: mcko sync with pull-down resistor vertical direction line identification pulse output/exposure time identification pulse output. switching possible using the serial interface data. (default: id) memory write timing pulse output. internal ssg enable. high: internal ssg valid, low: external sync valid with pull-down resistor 3.3v power supply. (power supply for common logic block) ccd reset gate pulse output. gnd ccd horizontal register clock output. 3.3v power supply. (power supply for h block) ccd horizontal register clock output. ccd horizontal register clock output. gnd ccd horizontal register clock output. 3.3v power supply. (power supply for h block) 3.3v power supply. (power supply for cds block) ccd precharge level sample-and-hold pulse output. ccd data level sample-and-hold pulse output. pulse output for horizontal and vertical blanking period pulse cleaning. ccd dummy signal clamp pulse output. ccd optical black signal clamp pulse output. the horizontal ob pattern can be changed using the serial interface data. clock output for analog/digital conversion ic. logical phase adjustment possible using the serial interface data. gnd inverter output. inverter input. ic test pin 1; normally fixed to gnd. with pull-down resistor ic test pin 2; normally fixed to gnd. with pull-down resistor 3.3v power supply. (power supply for common logic block) system clock output for signal processing ic. serial interface data input for internal mode settings. schmitt trigger input
? 5 ? cxD2498r pin no. symbol i/o description 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 sck sen vd hd v ss 5 vm v2 v4 v1a vh v1b v1c v3a vl v3b v3c sub i i i/o i/o ? ? o o o ? o o o ? o o o serial interface clock input for internal mode settings. schmitt trigger input serial interface strobe input for internal mode settings. schmitt trigger input vertical sync signal input/output. horizontal sync signal input/output. gnd gnd (gnd for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ccd vertical register clock output. 15.0v power supply. (power supply for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ccd vertical register clock output. ? 7.5v power supply. (power supply for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ccd electronic shutter pulse output.
? 6 ? cxD2498r electrical characteristics dc characteristics (within the recommended operating conditions) pins symbol item conditions min. max. unit supply voltage 1 supply voltage 2 supply voltage 3 input voltage 1 ? 1 input voltage 2 ? 2 input/output voltage output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 output voltage 6 output current 1 output current 2 v dd 2, v dd 3 v dd 4 v dd 1, v dd 5 rst, ssi, sck, sen test1, test2, sncsl, ssgsl vd, hd h1a, h1b, h2a, h2b rg xshp, xshd, pblk, obclp, clpdm, adclk cko mcko id/exp, wen v1a, v1b, v1c, v3a, v3b, v3c, v2, v4 sub v dd a v dd b v dd c vt + vt ? v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh3 v ol3 v oh5 v ol5 v oh6 v ol6 v oh7 v ol7 i ol i om1 i om2 i oh i osl i osh feed current where i oh = ? 1.2ma pull-in current where i ol = 2.4ma feed current where i oh = ? 3.3ma pull-in current where i ol = 2.4 ma feed current where i oh = ? 6.9ma pull-in current where i ol = 4.8ma feed current where i oh = ? 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = ? 2.4ma pull-in current where i ol = 4.8ma v1a/b/c, v2, v3a/b/c, v4 = ? 8.25v v1a/b/c, v2, v3a/b/c, v4 = ? 0.25v v1a/b/c, v3a/b/c = 0.25v v1a/b/c, v3a/b/c = 14.75v sub = ? 8.25v sub = 14.75v 3.0 3.0 3.0 0.8v dd c 0.7v dd c 0.8v dd c v dd c ? 0.8 v dd c ? 0.8 v dd c ? 0.8 v dd c ? 0.8 v dd c ? 0.8 10.0 5.0 5.4 3.6 3.6 3.6 0.2v dd c 0.2v dd c 0.2v dd c 0.4 0.4 0.4 0.4 0.4 ? 5.0 ? 7.2 ? 4.0 v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma ? 1 this input pin is a schmitt trigger input. ? 2 this input pin is with pull-down registor in the ic. v oh2 v ol2 feed current where i oh = ? 22.0ma pull-in current where i ol = 14.4ma 0.4 v v v dd a ? 0.8 feed current where i oh = ? 3.3ma pull-in current where i ol = 2.4ma v oh4 v ol4 v dd b ? 0.8 0.4 v v ty p . 3.3 3.3 3.3
? 7 ? cxD2498r inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) note) input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through a capacitor. switching characteristics (vh = 15.0v, vm = gnd, vl = ? 7.5v) note) 1) the mos structure of this ic has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) for noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1? or more) between each power supply pin (vh, vl) and gnd. 3) to protect the ccd image sensor, clamp the sub pin output at vh before input to the ccd image sensor. item pins symbol conditions min. typ. max. unit logical vth input voltage input amplitude cki lvth v ih v il v in fmax = 50mhz sine wave 0.7v dd c 0.3 v dd c/2 0.3v dd c v v v vp-p item symbol conditions min. typ. max. unit rise time fall time output noise voltage vl to vm vm to vh vl to vh vm to vl vh to vm vh to vl 350 350 60 350 350 60 500 500 90 500 500 90 1.0 1.0 1.0 1.0 ns ns ns ns ns ns v v v v ttlm ttmh ttlh ttml tthm tthl vclh vcll vcmh vcml 200 200 30 200 200 30
? 8 ? cxD2498r switching waveforms waveform noise v1a (v1b, v1c, v3a, v3b, v3c) v2 (v4) sub ttmh tthm vh vm vl vm vl vh vl 90% 10% 90% 10% ttlm ttlm 90% 10% 90% 10% ttlh tthl 90% 90% 10% 10% ttml 90% 10% ttml 90% 10% vcmh vcml vm vl vclh vcll
? 9 ? cxD2498r measurement circuit c1: 3300pf c2: 560pf c3: 820pf c4: 8pf c5: 320pf c6: 10pf r1: 30 ? r2: 10 ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vd cki c6 c6 c6 c6 c6 c6 c6 c6 c5 c5 c5 c5 c4 c3 cxD2498r serial interface data hd +3.3v ? 7.5v +15.0v c2 c2 c2 c2 c2 r1 r1 r1 r2 r1 r1 r1 c2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 c1 c2
? 10 ? cxD2498r ac characteristics ac characteristics between the serial interface clocks serial interface clock internal loading characteristics (1) symbol definition min. typ. max. unit t s1 t h1 sen setup time, activated by the falling edge of hd sen hold time, activated by the falling edge of hd 0 134 ns ? (within the recommended operating conditions) symbol definition min. typ. max. unit t s1 t h1 t s2 t s3 ssi setup time, activated by the rising edge of sck ssi hold time, activated by the rising edge of sck sck setup time, activated by the rising edge of sen sen setup time, activated by the rising edge of sck 20 20 20 20 ns ns ns ns (within the recommended operating conditions) ? restriction in draft mode with an operating frequency of 22.5mhz. ssi 0.2v dd c 0.2v dd c 0.8v dd c ts2 th1 ts1 ts3 0.8v dd c 0.8v dd c sck sen sen th1 enlarged view example: during frame mode 0.2v dd c ts1 0.2v dd c v1a vd hd hd v1a sen 0.8v dd c ? be sure to maintain a constantly high sen logic level near the falling edge of the hd in the horizontal period during which v1a/b/c and v3a/b/c values take the ternary value and during that horizontal period.
? 11 ? cxD2498r serial interface clock internal loading characteristics (2) symbol definition min. typ. max. unit t s1 t h1 sen setup time, activated by the falling edge of vd sen hold time, activated by the falling edge of vd 0 200 ns ns (within the recommended operating conditions) ? restriction with an operating frequency of 22.5mhz. th1 enlarged view 0.2v dd c ts1 0.2v dd c vd hd vd hd sen 0.8v dd c example: during frame mode ? be sure to maintain a constantly high sen logic level near the falling edge of vd. serial interface clock output variation characteristics normally, the serial interface data is loaded to the cxD2498r at the timing shown in ? serial interface clock internal loading characteristics (1) ? above. however, one exception to this is when the data such as stb is loaded to the cxD2498r and controlled at the rising edge of sen. see ? description of operation ? . 0.8v dd c sen output signal tpdpulse symbol definition min. typ. max. uniy t pdpulse output signal delay, activated by the rising edge of sen 5 ns (within the recommended operating conditions) 70
? 12 ? cxD2498r symbol definition min. typ. max. unit t w1 rst pulse width ns (within the recommended operating conditions) 22 rst loading characteristics rst 0.2v dd c tw1 0.8v dd c vd and hd phase characteristics (within the recommended operating conditions) vd hd ts1 th1 0.2v dd c 0.2v dd c 0.2v dd c symbol definition min. typ. max. unit t s1 t h1 vd setup time, activated by the falling edge of hd vd hold time, activated by the falling edge of hd 0ns ns 44 hd loading characteristics mcko load capacitance = 10pf (within the recommended operating conditions) hd mcko ts1 th1 0.2v dd d 0.8v dd d 0.2v dd d symbol definition min. typ. max. unit t s1 t h1 hd setup time, activated by the rising edge of mcko hd hold time, activated by the rising edge of mcko 31 0 ns ns
? 13 ? cxD2498r wen and id/exp load capacitance = 10pf (within the recommended operating conditions) output variation characteristics 0.8v dd c mcko wen, id/exp tpd1 symbol definition min. typ. max. unit t pd1 time until the above outputs change after the rise of mcko ns 23 33
? 14 ? cxD2498r description of operation pulses output from the cxD2498r are controlled mainly by the rst pin and by the serial interface data. the pin status table is shown below, and the details of serial interface control are described on the following pages. pin status table pin no. symbol cam slp stb rst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v ss 1 rst sncsl id/exp wen ssgsl v dd 1 rg v ss 2 h1a v dd 2 h1b h2a v ss 3 h2b v dd 3 v dd 4 xshp xshd pblk clpdm obclp adclk v ss 4 ? act act act l act act act act act l l l act l l l act act act act ? act l l act ? act l l act ? act l l act act l l act ? act l l act ? ? act l l act act l l act act l l h act l l h act l l h act l l act pin no. symbol cam slp stb rst 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cko cki test1 test2 vdd5 mcko ssi sck sen vd ? 1 hd ? 1 v ss 5 vm v2 v4 v1a vh v1b v1c v3a vl v3b v3c sub ? act act l act act act act act ? ? ? act act l act act act act dis act act act dis act act act dis act l l h act l l h ? ? act vm vm vm actvmvmvl act vh vh vm ? act vh vh vm act vh vh vm act vh vh vl ? act vh vh vl act vh vh vl act vh vh vl ? 1 it is for output. for input, all items are ? act ? . note) act means that the circuit is operating, and dis means that loading is stopped. l indicates a low output level, and h a high output level in the controlled status. also, vh, vm and vl indicate the voltage levels applied to vh (pin 41), vm (pin 37) and vl (pin 45), respectively, in the controlled status.
? 15 ? cxD2498r serial interface control the cxD2498r basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of hd. here, readout portion specifies the horizontal period during which v1a/b/c and v3a/b/c, etc. take the ternary value. note that some items reflect the serial interface data at the falling edge of vd or the rising edge of sen. ssi sck sen 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 these are two categories of serial interface data : the cxD2498r drive control data (hereafter ? control data ? ) and electronic shutter data (hereafter ? shutter data ? ). the details of each data are described below.
? 16 ? cxD2498r control data d00 to d07 d08 to d09 d10 to d11 d12 d13 d14 d15 d16 to d17 d18 to d32 d33 d34 to d35 d36 to d37 d38 to d39 d40 to d47 chip ctg mode ? smd htsg ? ptmd ? exp ptob ldad stb ? chip enable category switching drive mode switching ? electronic shutter mode switching ? 1 htsg control switching ? 1 ? drive mode pattern switching ? id/exp output switching obclp waveform pattern switching adclk logic phase adjustment standby control ? ? 1 see d13 smd. 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d11 mode. ?? off on off on ?? see d16 to d17 ptmd. ?? id exp see d34 to d35 ptob. see d36 to d37 ldad. see d38 to d39 stb. ?? data symbol function data = 0 data = 1 rst all 0 all 0 all 0 0 0 0 0 all 0 all 0 0 all 0 1 0 all 0 all 0
? 17 ? cxD2498r shutter data d00 to d07 d08 to d09 d10 to d19 d20 to d31 d32 to d41 d42 to d47 chip ctg svd shd spl ? chip enable category switching electronic shutter vertical period specification electronic shutter horizontal period specification high-speed shutter position specification 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d19 svd. see d20 to d31 shd. see d32 to d41 spl. ?? data symbol function data = 0 data = 1 rst all 0 all 0 all 0 all 0 all 0 0
? 18 ? cxD2498r detailed description of each data shared data: d08 to d09 ctg [category] of the data provided to the cxD2498r by the serial interface, the cxD2498r loads d10 and subsequent data to each data register as shown in the table below according to the combination of d08 and d09 . note that the cxD2498r can apply these categories consecutively within the same vertical period. however, care should be taken as the data is overwritten if the same category is applied. control data: d34 to d35 ptob [obclp waveform pattern] this specifies the obclp waveform pattern. the default is ? normal ? . see the timing charts for details. control data: d36 to d37 ldad [adclk logic phase] this indicates the adclk logic phase adjustment data. the default is 90 relative to mcko. control data: d38 to d39 stb [standby] the operating mode is switched as follows. however, the standby bits are loaded to the cxD2498r and control is applied immediately at the rising edge of sen. see the pin status table for the pin status in each mode. d09 d08 description of operation 0 0 1 0 1 x loading to control data register loading to shutter data register test mode d35 d34 waveform pattern 0 0 1 1 0 1 0 1 (normal) (rearward) (forward) (wide) d37 d36 degree of adjustment ( ) 0 0 1 1 0 1 0 1 0 90 180 270 d39 d38 symbol x 0 1 0 1 1 cam slp stb normal operating mode sleep mode standby mode operating mode
? 19 ? cxD2498r control data: [drive mode] the cxD2498r realizes various drive modes by using control data d10 to d11 mode and d16 to d17 ptmd. the drive mode bits are loaded to the cxD2498r and reflected at the falling edge of vd. these details are described below. first, the basic drive mode is assigned using the control data d10 to d11 mode. draft mode is the pulse eliminator drive mode called octuple speed mode in the icx282. this is a high frame rate drive mode that can be used for purposes such as monitoring and auto focus (af). progressive scan mode is the pulse eliminator drive mode called double speed mode (1) in the icx282. pulse elimination is performed, but the frame data is obtained over one field period and corresponds to progressive scan drive, so it is called progressive scan mode in this data sheet. double speed mode is the pulse eliminator drive mode called double speed mode (2) in the icx282. readout is applied with two lines added to provide an image which appears like frame mode with an increased frame rate. this drive mode is comprised of a and b fields, so when it is established, repeated drive is performed in the manner of a b a and so on. frame mode is the icx282 drive mode in which the data for all lines are read. this drive mode is also comprised of a and b fields, so when it is established, repeated drive is performed in the manner of a b a and so on like double speed mode. [special drive modes] of the above basic drive modes, when a drive mode other than double speed mode is specified, special drive modes can be specified using the control data d16 to d17 ptmd. see the timing charts for details of all drive modes. note that center scan modes (3) and (4) in the icx282 correspond to center scan 1 and 2 in frame mode, and center scan modes (1) and (2) in the icx282 correspond to center scan 1 and 2 in progressive scan mode. d11 d10 description of operation 0 0 1 1 0 1 0 1 draft mode (default) progressive scan mode double speed mode frame mode d17 d16 description of operation 0 1 1 x 0 1 draft mode draft mode af1 mode af2 mode progressive scan mode progressive scan mode center scan 1 mode center scan 2 mode frame mode frame mode center scan 1 mode center scan 2 mode
? 20 ? cxD2498r control data/shutter data: [electronic shutter] the cxD2498r realizes various electronic shutter functions by using control data d13 smd and d14 htsg and shutter data d10 to d19 svd, d20 to d31 shd and d32 to d41 spl. these functions are described in detail below. first, the various modes are shown below. these modes are switched using control data d13 smd. the electronic shutter data is expressed as shown in the table below using d20 to d31 shd as an example. however, msb (d31) is a reserve bit for the future specification, and it is handled as a dummy on this ic. [electronic shutter stopped mode] during this mode, all shutter data items are invalid. sub is not output in this mode, so the shutter speed is the accumulation time for one field. [electronic shutter mode] during this mode, the shutter data items have the following meanings. note) the bit data definition area is assured in terms of the cxD2498r functions, and does not assure the ccd characteristics. the period during which svd and shd are specified together is the shutter speed. an image of the exposure time calculation formula is shown below. in actual operation, the precise exposure time is calculated from the operating frequency, vd and hd periods, decoding value during the horizontal period, and other factors. (exposure time) = svd + {(number of hd per 1v) ? (shd + 1)} concretely, when specifying high-speed shutter, svd is set to ? 000h ? . (see the figure.) during low-speed shutter, or in other words when svd is set to ? 001h ? or higher, the serial interface data is not loaded until this period is finished. the vertical period indicated here corresponds to one field in each drive mode. in addition, the number of horizontal periods applied to shd can be considered as (number of sub pulses ? 1). d13 description of operation 0 1 electronic shutter stopped mode electronic shutter mode msb d31 d30 d29 d28 lsb d23 d22 d21 d20 x001 0011 13 shd is expressed as 1c3h . d27 d26 d25 d24 1100 c symbol data description svd shd spl d10 to d19 d20 to d31 d32 to d41 number of vertical periods specification (000h svd 3ffh) number of horizontal periods specification (000h shd 7ffh) vertical period specification for high-speed shutter operation (000h spl 3ffh)
? 21 ? cxD2498r further, spl can be used during this mode to specify the sub output at the desired vertical period during the low-speed shutter period. in the case below, sub is output based on shd at the spl vertical period out of (svd + 1) vertical periods. incidentally, spl is counted as ? 000h ? , ? 001h ? , ? 002h ? and so on in conformance with svd. using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. 11 001h 000h 10fh 0a3h shd vd v1a sub wen exp smd svd 002 001 spl 000 spl shd exposure time 002h 000h svd 11 002h 000h 10fh 050h shd vd v1a sub wen exp smd svd svd shd exposure time
? 22 ? cxD2498r [htsg control mode] this mode controls the v1a/b/c and v3a/b/c ternary level outputs (readout pulse block) using d14 htsg. when control is applied, v pulse modulation does not occur during the readout period, and only normal v transfer is performed. [exp pulse] the id/exp pin (pin 4) output can be switched between the id pulse or the exp pulse using d33 exp. the default is the ? id ? pulse. see the timing charts for the id pulse. the exp pulse indicates the exposure time when it is high. the transition point is midpoint value (1515ck) of the last sub pulse falling edge and each v1a/ b/c and v3a/b/c ternary output falling edge. when there is no sub pulse, the later ternary output falling edge (1590ck) is used. see the exp pulse indicated in the explanatory diagrams under [electronic shutter] for an image of operation. d14 description of operation 0 1 readout pulse (sg) normal operation htsg control mode 10 0 0 1 1 vd v1a vck sub wen exp htsg smd exposure time
? 23 ? cxD2498r chart-1 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 1059h in the a field and 1017h in the b field (2894ck in both cases). the b field 1016h only has a 950ck pe riod. mode frame mode applicable ccd image sensor icx282 d high-speed sweep block high-speed sweep block c 1 12732 b hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen 73 78 1059 3 157 13579111315 1941 1943 1945 1947 1949 1951 1953 1955 1957 1959 1952 1954 1956 1958 1960 246 8 2 4 6 8 10 12 a 1013 1017 a field b field
? 24 ? cxD2498r c high-speed sweep block high-speed sweep block c 1 14954 e hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen 1038 49 54 1038 256 12569101314 1946 1949 1950 1953 1954 1957 1958 1949 1950 1953 1954 1957 1958 256 125691013 e chart-2 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 1038h period (2894ck). 1037h only has a 1922ck period. mode progressive scan mode applicable ccd image sensor icx282
? 25 ? cxD2498r i high-speed sweep block high-speed sweep block h 1 12528 g hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen 69 72 563 7 3 37 5 1 15 913172125293337 11 15 19 23 27 31 35 39 48 26 12 16 20 24 28 32 10 14 48 2 6 18 22 26 30 f 519 527 a field b field 1958 1960 1949 1953 1957 1951 1955 1959 chart-3 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 563h in the a field and 527h in the b field (3102ck in both cases). the b field 525h has a 1700ck period an d 526h has a 1699ck period. mode double speed mode applicable ccd image sensor icx282
? 26 ? cxD2498r 12 12 hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen 249 6 514 2 110 17 26 33 21 30 37 514 110 17 26 33 21 30 37 6 2 249 1953 1957 1946 1950 1937 1941 1937 1946 1953 1941 1950 1957 j j chart-4 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 249h (3022ck) period. 248h only has a 1294ck period. mode draft mode applicable ccd image sensor icx282
? 27 ? cxD2498r d high-speed sweep block high-speed sweep block c a field b field 1 91 12545 k bk hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen frame shift block frame shift block 530 71 576 1 497 499 501 2 498 a chart-5 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 576h in the a field and 530h in the b field (2894ck in both cases). mode frame mode (center scan 1) applicable ccd image sensor icx282
? 28 ? cxD2498r d high-speed sweep block high-speed sweep block c a field b field 1 100 12554 k bk hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen frame shift block frame shift block 302 71 347 1 735 737 739 2 736 a chart-6 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 347h in the a field and 302h in the b field (2894ck in both cases). the b field 301h only has a 1563ck peri od. mode frame mode (center scan 2) applicable ccd image sensor icx282
? 29 ? cxD2498r c high-speed sweep block high-speed sweep block c 1 33 11233 k k hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen frame shift block frame shift block 519 12 519 2 501 502 505 2 501 502 e e chart-7 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 519h (2894ck) period. 518h only has a 2408ck period. mode progressive scan mode (center scan 1) applicable ccd image sensor icx282
? 30 ? cxD2498r c high-speed sweep block high-speed sweep block c 1 47 11747 k ek hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen frame shift block frame shift block 295 17 295 2 737 738 741 2 737 738 e chart-8 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 295h (2894ck) period. mode progressive scan mode (center scan 2) applicable ccd image sensor icx282
? 31 ? cxD2498r high-speed sweep block high-speed sweep block 1 19 19 l jl hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen frame shift block frame shift block 125 19 9 125 6 2 561 570 577 565 574 581 561 570 577 565 574 581 2 6 j m m chart-9 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 125h (3022ck) period. 124h only has a 647ck period. mode draft mode (af1) applicable ccd image sensor icx282
? 32 ? cxD2498r high-speed sweep block high-speed sweep block 1 27 113 l jl hd sub vd v1a v3a v3b v3c v4 v1b v1c v2 ccd out pblk obclp id/exp clpdm wen frame shift block frame shift block 63 13 63 6 2 849 858 865 853 862 869 2 6 j m m chart-10 vertical direction timing chart ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is 63h (3022ck) period. 62h only has a 324ck period. mode draft mode (af2) applicable ccd image sensor icx282
? 33 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (2894) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 pblk obclp (1) 24 obclp (2) 16 obclp (3) obclp (4) 115 16 clpdm v3a/b/c v4 245 115 sub 4 id/exp 115 wen 62 298 310 314 270 89 166 219 141 193 296 234 176 62 52 44 60 32 60 296 272 62 chart-11 horizontal direction timing chart ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows a peri od of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp and wen are output at the timing shown above at the position shown in chart-1, 2, 5, 6, 7 and 8. mode frame mode (including center scan 1 and 2) progressive scan mode (including center scan 1 and 2) applicable ccd image sensor icx282
? 34 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (3102) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 pblk obclp (1) 24 obclp (2) 16 obclp (3) obclp (4) 115 16 clpdm v3a/b/c v4 245 115 sub 4 id/exp 115 wen 62 506 518 522 478 89 166 219 141 193 504 442 384 62 52 44 60 32 60 504 480 453 323 297 374 427 349 401 270 62 chart-12 horizontal direction timing chart ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows a peri od of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp and wen are output at the timing shown above at the position shown in chart-3. mode double speed mode applicable ccd image sensor icx282
? 35 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (3022) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 pblk obclp (1) 24 obclp (2) 16 obclp (3) obclp (4) 115 16 clpdm v3a/b/c v4 84 sub 4 id/exp 115 wen 62 426 438 442 398 73 104 126 94 115 424 365 307 62 52 44 60 32 60 424 400 62 136 168 157 188 210 178 146 220 252 241 272 294 262 230 304 336 325 356 378 346 388 367 283 314 199 chart-13 horizontal direction timing chart ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows a peri od of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp and wen are output at the timing shown above at the position shown in chart-4, 9 and 10. mode draft mode (including af1 and 2) applicable ccd image sensor icx282
? 36 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (2894) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 clpdm v3a/b/c v4 4 id/exp 115 wen 62 298 310 314 270 62 114 140 88 166 218 244 192 270 322 348 296 374 426 452 400 478 530 62 114 166 218 270 322 374 426 478 530 556 504 140 88 244 192 348 296 452 400 556 #5 #4 #3 #2 #1 504 pblk obclp 24 sub 234 176 62 52 chart-14 horizontal direction timing chart (high-speed sweep: c) ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? pblk, obclp, id/exp and wen are output at the timing shown above at the position shown in chart-1, 2, 5, 6, 7 and 8. ? high-speed sweep of v1a/b/c, v2, v3a/b/c and v4 is performed up to 70h 2362ck (#1970) in the a field of frame mode (including c enter scan 1 and 2), 47h 2884ck (#1335) in progressive scan mode, 10h 2842ck (#305) in progressive scan mode (center scan 1), and 16h 2846ck (#472) in progressive scan mo de (center scan 2). mode frame mode (including center scan 1 and 2) progressive scan mode (including center scan 1 and 2) applicable ccd image sensor icx282
? 37 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (2894) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 clpdm v3a/b/c v4 4 id/exp 115 wen 62 298 310 314 270 62 170 134 98 206 278 242 314 350 386 458 422 494 530 #7 #6 #5 #4 #3 #2 #1 pblk obclp 24 sub 234 176 62 52 62 170 98 206 278 242 314 386 458 494 530 80 188 152 116 224 296 260 332 368 404 476 440 512 548 80 188 152 116 224 296 260 332 368 404 476 440 512 548 422 350 134 chart-15 horizontal direction timing chart (high-speed sweep: d) ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? pblk, id/exp and wen are output at the timing shown above at the position shown in chart-1, 5, and 6. ? high-speed sweep of v1a/b/c, v2, v3a/b/c and v4 is performed up to 24h 1670ck (#986) in the b field of frame mode (including ce nter scan 1 and 2). mode frame mode (including center scan 1 and 2) applicable ccd image sensor icx282
? 38 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (3102) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 clpdm v3a/b/c v4 4 id/exp wen 62 506 518 522 478 114 166 218 270 322 374 426 478 530 62 114 166 218 322 426 530 88 140 192 244 296 348 452 504 556 #5 #3 #2 #1 pblk obclp sub 384 442 400 88 140 192 244 296 348 452 504 556 400 62 374 270 478 #4 chart-16 horizontal direction timing chart (high-speed sweep: h) ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? high-speed sweep of v1a/b/c, v2, v3a/b/c and v4 is performed up to 66h 314ck (#1970). mode double speed mode applicable ccd image sensor icx282
? 39 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (3102) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 clpdm v3a/b/c v4 4 id/exp wen 62 506 518 522 478 98 134 170 206 278 242 314 350 386 422 494 458 530 80 116 152 188 224 260 332 368 404 440 476 512 548 #7 #6 #5 #4 #3 #2 #1 pblk obclp sub 384 442 296 62 98 134 170 206 278 242 314 350 386 422 494 458 530 62 62 24 52 80 116 152 188 224 260 332 368 404 440 476 512 548 296 chart-17 horizontal direction timing chart (high-speed sweep: i) ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? high-speed sweep of v1a/b/c, v2, v3a/b/c and v4 is performed up to 22h 2810ck (#986). mode double speed mode applicable ccd image sensor icx282
? 40 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (3022) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 clpdm v3a/b/c v4 4 id/exp wen 62 426 438 442 398 73 104 157 188 241 272 325 356 409 440 493 524 94 126 178 210 262 294 346 378 430 462 514 546 115 146 199 283 367 451 535 84 136 168 220 252 304 336 388 420 472 556 #5 #6 #4 #3 #2 #1 pblk obclp sub 365 307 482 398 314 230 62 504 chart-18 horizontal direction timing chart (high-speed sweep: m) ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? high-speed sweep of v1a/b/c, v2, v3a/b/c and v4 is performed up to 7h 2848ck (#285) in draft mode (af1), 11h 2184ck (#421) in d raft mode (af2). mode draft mode (af1 and 2) applicable ccd image sensor icx282
? 41 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (2894) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 clpdm v3a/b/c v4 4 id/exp wen 62 298 310 314 270 89 166 297 374 505 193 401 115 245 323 453 531 141 219 349 427 #3 #2 #1 pblk obclp sub 234 176 62 478 557 270 chart-19 horizontal direction timing chart (frame shift : k) ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows a peri od of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? frame shift of v1a/b/c, v2, v3a/b/c and v4 is performed up to 90h 2864ck (#250) in the a field of frame mode (center scan 1), 4 4h 2864ck (#250) in the b field, 99h 1570ck (#369) in the a field of frame mode (center scan 2), 53h 1570ck (#369) in the b field, 32h 2864ck (#250) in progressive scan mo de (center scan 1), and 46h 1646ck (#369) in progressive scan mode (center scan 2). mode frame mode (including center scan 1 and 2) progressive scan mode (including center scan 1 and 2) applicable ccd image sensor icx282
? 42 ? cxD2498r mcko h2a/b v1a/b/c h1a/b (3022) 0 50 100 150 200 250 300 350 400 450 500 550 hd v2 clpdm v3a/b/c v4 4 id/exp wen 62 426 438 442 398 73 104 157 188 241 272 325 356 409 440 493 94 126 178 210 262 294 346 378 430 462 514 546 115 146 199 283 367 451 535 84 136 168 220 252 304 336 388 420 472 556 #5 #6 #4 #3 #2 #1 pblk obclp sub 365 307 482 398 314 230 62 504 524 chart-20 horizontal direction timing chart (frame shift: l) ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? frame shift of v1a/b/c, v2, v3a/b/c and v4 is performed up to 18h 2092ck (#276) in draft mode (af1), 22h 2100ck (#420) in draft mode (af2). mode draft mode (af1 and 2) applicable ccd image sensor icx282
? 43 ? cxD2498r hd [a field] [b field] a b v3b v3c v3b v3c v1a v1b v1c v3a v1a v1b v1c v3a (2894) 0 62 89 115 141 166 193 219 245 270 297 323 (2894) 0 62 89 115 141 166 193 219 245 1380 v2 v4 v2 v4 1410 1440 1470 1530 1560 1590 1620 1650 1680 1710 logic alignment portion chart-21 horizontal direction timing chart ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. mode frame mode (including center scan 1 and 2) applicable ccd image sensor icx282
? 44 ? cxD2498r hd e v3b v1a v1b v1c v3c v3a (2894) 0 62 89 115 141 166 193 219 245 270 297 323 (2894) 0 62 89 115 141 166 193 219 245 1380 v2 1410 1440 1470 1530 1500 1560 1590 1620 1650 1680 1710 v4 chart-22 horizontal direction timing chart ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. mode progressive scan mode (including center scan 1 and 2) applicable ccd image sensor icx282
? 45 ? cxD2498r hd [a field] [b field] v3a v3b v3c v1a v1b v1c v1a v1b v1c v3b v3c v3a (3102) 0 62 89 115 141 166 193 219 245 270 297 323 349 374 401 427 453 478 505 531 (3102) 0 62 89 115 141 166 193 219 245 270 297 323 349 374 1380 v2 v4 v2 v4 1410 1440 1470 1530 1560 1590 1620 1650 1680 1710 logic alignment portion f g chart-23 horizontal direction timing chart ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. mode double speed mode applicable ccd image sensor icx282
? 46 ? cxD2498r hd (3022) 0 62 73 84 94 104 115 126 136 146 157 168 178 188 199 210 220 230 241 252 262 272 283 294 304 314 325 336 346 356 367 378 388 62 73 84 94 104 115 126 136 146 157 168 178 188 199 210 220 230 241 252 262 272 283 294 304 314 (3022) 0 1290 1320 1350 1380 1410 1440 1470 1500 1530 1560 1590 j v1a v1b v1c v3a v3b v3c v4 v2 chart-24 horizontal direction timing chart ? the hd of this chart indicates the actual cxD2498r load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.8 to 12.0? (when the drive frequency is 22.5mhz). this chart shows an per iod of 115ck (5.1?). internal ssg is at this timing. mode draft mode (including af1 and 2) applicable ccd image sensor icx282
? 47 ? cxD2498r hd hd' cki cko adclk mcko h1a/b h2a/b rg xshp xshd 62 1 270/398/478 chart-25 high-speed phase timing chart ? hd ? indicates the hd which is the actual cxD2498r load timing. ? the phase relationship of each pulse shows the logical position relationship. for the actual output waveform, a delay is added to each pulse. ? the logical phase of adclk can be specified by the serial interface data. mode applicable ccd image sensor icx282
? 48 ? cxD2498r v1a v1b v1c v2 v3b v3c v4 v3a sub mechanical shutter close open ccd out abc ee f mode 0 0000 3 3 0 0 vd exposure time abcde f chart-a1 vertical direction sequence chart ? this chart is a drive timing chart example of electronic shutter normal operation. ? data exposed at d includes the blooming component. for details, see the ccd image sensor data sheet. ? the cxD2498r does not generate the pulse to control mechanical shutter operation. ? the switching timing of drive mode and electronic shutter data are not the same. mode draft frame (or double speed) draft applicable ccd image sensor icx282
? 49 ? cxD2498r v1a v1b v1c v2 v3b v3c v4 v3a sub close open ccd out abc ef g h mode 0 0000 1 00 0 0 vd exposure time abcd eh f g mechanical shutter chart-a2 vertical direction sequence chart ? this chart is a drive timing chart example of electronic shutter normal operation. ? data exposed at d includes the blooming component. for details, see the ccd image sensor data sheet. ? the cxD2498r does not generate the pulse to control mechanical shutter operation. ? the switching timing of drive mode and electronic shutter data are not the same. mode draft progressive scan draft applicable ccd image sensor icx282
? 50 ? cxD2498r application circuit block diagram notes for power-on of the three ? 7.5v, +15.0v, +3.3v power supplies, be sure to start up the ? 7.5v and +15.0v power supplies in the following order to prevent the sub pin of the ccd image sensor from going to negative potential. t1 t2 15.0v 0v ? 7.5v 20% 20% t2 t1 26 27 28 31 32 34 35 30 25 23 22 21 20 19 18 mcko vd hd cko adclk obclp clpdm pblk xshd xshp sck 33 sen ssi test2 test1 cki ccd out digital out v-dr ssg 6 3 2 5 4 ssgsl sncsl rst wen id/exp 12 15 8 rg h2b 13 h2a h1b 10 h1a 40 42 38 v2 v1b 43 v1c v1a 44 46 39 v4 48 sub v3b 47 v3c v3a ccd icx282 cds/adc block tg cxD2498r controller vco signal processor block application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 51 ? cxD2498r sony corporation package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ? 0.03 + 0.08 0.2g lqfp-48p-l01 lqfp048-p-0707 (8.0) 0.5 0.2 0.127 ? 0.02 + 0.05 a 1.5 ? 0.1 + 0.2 0.1 palladium plating note: dimension ? ? ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b :palladium 0.127 0.04 0.18 0.03

▲Up To Search▲

Price & Availability of D2498

	To Download D2498 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .